• DocumentCode
    951465
  • Title

    An efficient scaling procedure for domain CMOS logic

  • Author

    Wurtz, Larry T.

  • Author_Institution
    Dept. of Electr. Eng., Alabama Univ., Tuscaloosa, AL, USA
  • Volume
    28
  • Issue
    9
  • fYear
    1993
  • fDate
    9/1/1993 12:00:00 AM
  • Firstpage
    979
  • Lastpage
    982
  • Abstract
    The layout area required by a domino CMOS gate to support a specific response-time performance for a particular capacitive load can be substantially reduced by scaling the NFET chain. A scaling procedure that requires little execution time is described and illustrated by its application to AND, AOI, and OAI domino CMOS gates. The procedure is equally applicable to other forms of dynamics logic
  • Keywords
    CMOS integrated circuits; integrated logic circuits; logic design; logic gates; CMOS gates; NFET chain; domain CMOS logic; layout area; scaling procedure; CMOS logic circuits; CMOS process; Delay effects; Fabrication; Inverters; Parasitic capacitance; SPICE; Very large scale integration;
  • fLanguage
    English
  • Journal_Title
    Solid-State Circuits, IEEE Journal of
  • Publisher
    ieee
  • ISSN
    0018-9200
  • Type

    jour

  • DOI
    10.1109/4.236178
  • Filename
    236178
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=951465