Design and Performance of a System for VLSI Packaging Thermal Modeling and Characterization

The problem of thermal performance evaluation of Level 1 (chip and carrier) and Level 2 (boards/modules, interconnections) VLSI packaging structures is addressed. Developed modeling and characterization tools are discussed. Thermal modeling/simulation in Level 1 and Level 2 VLS1 packaging structures is approached through the development of a thermal and thermally induced stress modeling/simulation system. The system includes preprocessors and postprocessors for use with common-core numerical solution codes ("number crunchers") to perform thermal and thermally induced displacement and stress analysis of VLSI-based packaging structures. It also includes an internal databank with a material data list, thermal and thermal-mechanical models applicable to VLSI packages, and a library of analyzed structures (models). The system is called the packaging thermal mechanical calculator (PTMC). Thermal characterization of Level 1 and Level 2 VLSI packaging structures is approached through the development of a thermal characterization station, which has the form of the computer controlled thermal characterization system (CCTCS) designed to measure steady-state and temperature transients in devices, circuits, and packages. AS part of the system, specially designed thermal test chips are introduced to measure thermal response in packaged chips with nonuniform power distribution. The overall modeling and characterization system, in a modular form, is general and expandable as packaging and interconnection technology evolves. Examples of practical implementation of the proposed concepts will be given.