VLSI Chip Interconnection Technology Using Stacked Solder Bumps

A new type of flip-chip interconnection technology using stacked solder bumps supposed by polyimide films has been developed to improve the reliability of large-size VLSI chip interconnections. This technology is based on the principle that the higher the equivalent bump height; the smaller will be the shear strain. Numerical analysis shows that the increased number Of solder bump stacks reduces the shear strain in solder joints. In particular, thermal shock test results indicate that the lifetime of the double-stacked solder bumps joining 20 x 20-mm silicon chips to alumina ceramic boards is 60 times that of conventional . . unstacked bumps.