• DocumentCode
    952405
  • Title

    Electrical properties of silicon-implanted furnace-annealed silicon-on-sapphire devices

  • Author

    Roulet, M.E. ; Schwob, P. ; Golecki, I. ; Nicolet, M.-A.

  • Author_Institution
    Centre Electronique Horloger SA, Neuchâtel, Switzerland
  • Volume
    15
  • Issue
    17
  • fYear
    1979
  • Firstpage
    527
  • Lastpage
    529
  • Abstract
    The crystalline quality of s.o.s. layers can be improved near the silicon-sapphire interface by silicon implantation followed by recrystallisation. Device performance on such layers is markedly improved as to n-channel m.o.s.t. noise and leakage current, reverse diode current and lateral bipolar transistor gain. Minority-carrier lifetimes up to 50 ns are deduced.
  • Keywords
    annealing; bipolar transistors; electron device noise; insulated gate field effect transistors; integrated circuit technology; ion implantation; semiconductor diodes; semiconductor epitaxial layers; 50 ns minority carrier lifetime; SOS layers crystalline quality improvement; Si implanted furnace annealed SOS devices; Si sapphire interface; electrical properties; lateral bipolar transistor gain; leakage current; n-channel MOS transistor noise; reverse diode current;
  • fLanguage
    English
  • Journal_Title
    Electronics Letters
  • Publisher
    iet
  • ISSN
    0013-5194
  • Type

    jour

  • DOI
    10.1049/el:19790380
  • Filename
    4243501
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=952405