DocumentCode
952627
Title
LSI Yield Projections Based Upon Test Pattern Results: An Application to Multilevel Metal Structures
Author
Turley, A. ; Herman, David
Author_Institution
Westinghouse Electric Corporation, Baltimore, MD
Volume
10
Issue
4
fYear
1974
fDate
12/1/1974 12:00:00 AM
Firstpage
230
Lastpage
234
Abstract
Practical methods for making LSl yield projections are described in detail. The application of these methods to multilevel metal structures in particular is presented by means of example calculations of yield based on test pattern data. Using these methods the yield of any general multilevel metal interconnection pattern can be projected. It is shown that structural density, rather than chip area alone, should be the prime consideration in yield predictions.
Keywords
Integrated circuit interconnections; Interconnections, Integrated circuits; LSI; Circuits; Degradation; Dielectrics; Differential equations; Insulation; Large scale integration; Metal-insulator structures; Testing;
fLanguage
English
Journal_Title
Parts, Hybrids, and Packaging, IEEE Transactions on
Publisher
ieee
ISSN
0361-1000
Type
jour
DOI
10.1109/TPHP.1974.1134868
Filename
1134868
Link To Document