Modeling of charge trapping induced threshold-voltage instability in high-κ gate dielectric FETs

The authors have developed a distributed tunneling model to investigate the threshold-voltage instability induced by charge trapping in field-effect transistors (FETs) using high-κ gate dielectric materials. The charge trapping dynamics in the high-κ layer are modeled based on a rate equation, which is self-consistently incorporated into device-level simulations. The model is used to simulate pulsed operation of HfO₂ based n-type FETs; good agreement is obtained with pulsed measurements including the dependence of the threshold-voltage shift on pulse heights and durations. The trap-energy-level shift due to the polaron effect is found to be critical to model the pulse-height dependence of the threshold-voltage shift.