DocumentCode
952850
Title
Gate-dielectric permitivity and metal-gate work-function tradeoff in Lmet=25nm PDSOI device characteristics
Author
Guo, Dechao ; Bryant, Andres ; Wang, Xinlin ; Narasimha, Shreesh ; Miller, Robert ; Khare, Mukesh
Author_Institution
Dept. of Electr. Eng., Yale Univ., New Haven, CT, USA
Volume
27
Issue
6
fYear
2006
fDate
6/1/2006 12:00:00 AM
Firstpage
505
Lastpage
507
Abstract
Short-channel (L=25nm) silicon-on-insulator (SOI) device performances over a range of gate work function from band edge to midgap and a range of gate-dielectric permittivity from 3.9 to 15 are studied using a two-dimensional simulator that takes into account quantum-mechanical effects. A tradeoff between metal-gate work-function requirements, gate-dielectric permittivity, and device design criteria is presented. For a high-performance device design criteria, device performance benefits are also quantified as a function of gate work function and gate-dielectric permittivity. The results suggest that the maximum benefits can be obtained even when the metal-gate work function is within 110 meV (90 meV) below (above) the conduction (valence) band edge for 25-nm SOI nMOSFETs (pMOSFETs).
Keywords
MOSFET; permittivity; semiconductor device models; silicon-on-insulator; work function; 25 nm; PDSOI; gate dielectric permittivity; high performance device design; metal-gate work-function; nMOSFET; quantum-mechanical effect; CMOS technology; Dielectric devices; Dielectric materials; Electrodes; Inorganic materials; MOSFETs; Performance evaluation; Permittivity; Semiconductor materials; Silicon on insulator technology; Conduction band edge (CBE); drain-induced barrier lowering (DIBL); high-; metal gate; partially depleted (PD); short channel; silicon-on-insulator (SOI); subthreshold swing (SS); work function;
fLanguage
English
Journal_Title
Electron Device Letters, IEEE
Publisher
ieee
ISSN
0741-3106
Type
jour
DOI
10.1109/LED.2006.875757
Filename
1637571
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