DocumentCode :
952980
Title :
Systolic array architecture for Gabor decomposition
Author :
Iyengar, G. ; Panchanathan, S.
Author_Institution :
Media Lab., MIT, Cambridge, MA, USA
Volume :
5
Issue :
4
fYear :
1995
fDate :
8/1/1995 12:00:00 AM
Firstpage :
355
Lastpage :
359
Abstract :
We propose a combined systolic array-content addressable memory architecture for real-time Gabor decomposition. We then present codec designs for progressive image transmission using this architecture. Gabor decomposition is attractive for image compression since the basis functions match the human visual profiles. Gabor functions also achieve the lowest bound on the joint uncertainty of data. However these functions are not orthogonal and hence an analytic solution for tire decomposition does not exist. It has been shown that Gabor decomposition can be computed as a multiplication between a transform matrix and a vector of the image data. For an n×n image, the proposed architecture for Gabor decomposition consists of a linear systolic array of n processing elements each with a local CAM. Simulations and complexity studies show that this architecture can achieve real-time performance with current VLSI technology
Keywords :
VLSI; codecs; content-addressable storage; data compression; image coding; memory architecture; systolic arrays; VLSI technology; basis functions; complexity; content addressable memory; human visual profiles; image compression; image data vector; joint data uncertainty; linear systolic array; multiplication; processing elements; real-time Gabor decomposition; real-time performance; simulations; systolic array architecture; transform matrix; Codecs; Computer architecture; Humans; Image coding; Image communication; Matrix decomposition; Memory architecture; Systolic arrays; Tires; Uncertainty;
fLanguage :
English
Journal_Title :
Circuits and Systems for Video Technology, IEEE Transactions on
Publisher :
ieee
ISSN :
1051-8215
Type :
jour
DOI :
10.1109/76.465089
Filename :
465089
Link To Document :
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