A 1-V 24-GHz 17.5-mW phase-locked loop in a 0.18-μm CMOS process

Author

Ng, Alan W L ; Leung, Gerry C T ; Kwok, Ka-Chun ; Leung, Lincoln L K ; Luong, Howard C.

Author_Institution

Dept. of Electr. & Electron. Eng., Hong Kong Univ. of Sci. & Technol., China

Volume

41

Issue

6

fYear

2006

fDate

6/1/2006 12:00:00 AM

Firstpage

1236

Lastpage

1244

Abstract

A 1-V 24-GHz 17.5-mW fully integrated phase-locked loop employing a transformer-feedback voltage-controlled oscillator and a stacked divide-by-2 frequency divider for low voltage and low power is presented. Implemented in a 0.18-μm CMOS process and operated at 24 GHz with a 1-V supply, the PLL measures in-band phase noise of -106.3 dBc at a frequency offset of 100 kHz and out-of-band phase noise of -119.1 dBc/Hz at a frequency offset of 10 MHz. The PLL dissipates 17.5 mW and occupies a core area of 0.55 mm².

Keywords

CMOS integrated circuits; low-power electronics; phase locked loops; voltage-controlled oscillators; -106.3 dB; 0.18 micron; 1 V; 10 MHz; 100 kHz; 17.5 mW; 24 GHz; CMOS process; clock generation; frequency divider; phase-locked loop; synthesizer; transceiver; transformer-feedback; voltage controlled oscillator; CMOS process; Circuits; Energy consumption; Frequency conversion; Low voltage; Phase locked loops; Phase noise; Radio frequency; Signal to noise ratio; Voltage-controlled oscillators; Clock generation; low power; low voltage; oscillator; phase-locked loop (PLL); receiver; synthesizer; transceiver; transformer; voltage-controlled oscillator (VCO);

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.2006.874332

Filename

1637588