The design and analysis of a DLL-based frequency synthesizer for UWB application

Author

Lee, Tai-Cheng ; Hsiao, Keng-Jan

Author_Institution

Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan

Volume

41

Issue

6

fYear

2006

fDate

6/1/2006 12:00:00 AM

Firstpage

1245

Lastpage

1252

Abstract

A delay-locked loop (DLL)-based frequency synthesizer is designed for the ultrawideband (UWB) Mode-1 system. This frequency synthesizer with 528-MHz input reference frequency achieves less than 9.5-ns settling time by utilizing wide loop bandwidth and fast-settling architecture. Additionally, a discrete-time model of the DLL and an analytical model of phase noise of the delay line are proposed in this work. Experimental results show great consistency with predicted settling time and phase noise. The circuit has been fabricated in a 0.18-μm CMOS technology and consumes only 54 mW from a 1.8-V supply. It exhibits a sideband magnitude of -35.4 dBc and -120-dBc/Hz phase noise at the frequency offset of 1 MHz.

Keywords

CMOS integrated circuits; UHF integrated circuits; delay lock loops; frequency synthesizers; ultra wideband communication; -120 dB; -35.4 dB; 1 MHz; 1.8 V; 528 MHz; 54 mW; 9.5 ns; CMOS technology; DLL; UWB application; delay line; delay-locked loop; fast-settling architecture; frequency multiplier; frequency synthesizer; ultrawideband Mode-1 system; Amplitude modulation; Bandwidth; CMOS technology; Circuits; Clocks; Delay lines; FCC; Frequency locked loops; Frequency synthesizers; Phase noise; Delay-locked loops; frequency multiplier; phase noise;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.2006.874353

Filename

1637589