All-digital delay-locked loop/pulsewidth-control loop with adjustable duty cycles

Author

Wang, You-Jen ; Kao, Shao-Ku ; Liu, Shen-Iuan

Author_Institution

Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan

Volume

41

Issue

6

fYear

2006

fDate

6/1/2006 12:00:00 AM

Firstpage

1262

Lastpage

1274

Abstract

An all-digital delay-locked loop (DLL) and an all-digital pulsewidth-control loop (PWCL) with adjustable duty cycles are presented. For the DLL, by using the flash time-to-digital conversion, both the phase alignment and the duty cycle of the output clock are assured in 10 cycles. For the PWCL, the sequential time-to-digital conversion is adopted to reduce the required D-flip-flops and lock within 28 cycles. For both of the proposed circuits, the requirement of the input clock with 50% duty cycle is eliminated. The proposed circuits have been fabricated in a 0.35-μm CMOS process. The proposed DLL generates the output clock with the duty cycle of 25%, 50% and 75%, and the operation frequency range is from 140 to 260 MHz. For the proposed PWCL, the duty cycle is adjusted from 30% to 70% in steps of 10%. The operation frequency range is from 400 to 600 MHz.

Keywords

CMOS digital integrated circuits; delay lock loops; digital integrated circuits; pulse width modulation; 140 MHz; 260 MHz; CMOS process; DLL; PWCL; adjustable duty cycles; delay-locked loop; flash time-to-digital conversion; pulsewidth-control loop; sequential time-to-digital conversion; CMOS process; CMOS technology; Circuits; Clocks; Delay lines; Frequency; Power dissipation; Space vector pulse width modulation; Timing jitter; Voltage; Delay-locked loop (DLL); duty cycle and time-to-digital conversion; pulsewidth control loop;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.2006.874326

Filename

1637591