Title :
Baseband and audio mixed-signal front-end IC for GSM/EDGE applications
Author :
Baggini, Barbara ; Basedau, Philipp ; Becker, Rolf ; Bode, Peter ; Burdenski, Ralf ; Esfahani, Farzad ; Groeneweg, Willem ; Helfenstein, Markus ; Lampe, Alexander ; Ryter, Roland ; Stephan, Ralph
Author_Institution :
Bus. Line Cellular Syst., Philips Semicond., Zurich, Switzerland
fDate :
6/1/2006 12:00:00 AM
Abstract :
A complete mixed-signal front-end CMOS chip is presented, supporting GSM/EDGE as well as enhanced audio applications. The chosen solution for the transmit section is based on Laurent´s approximation of the nonlinear GMSK modulator. This enables burst shaping in the I/Q domain thereby solving the problem of power ramping. Also, up to GPRS class 12 is supported. The receive section on the other hand consists of a low power dual mode continuous-time ΣΔ ADC for I and Q, supporting ZIF and LIF modes of operation and achieving typically 12.5 bit of resolution under production conditions. An on-chip PLL, which supplies all blocks with various clock frequencies, additionally supports clock jitter suppression. The audio section comprises a codec supporting standard formats such as IIS and PCM. It features mono/stereo signaling from various sources in 16bit quality as well as high-drive buffers for 4 Ω single-ended loads (capacitively coupled). The whole chip is powered from a 1.5/2.65 V supply voltage and consumes 22 mW in paging mode.
Keywords :
CMOS integrated circuits; cellular radio; codecs; jitter; minimum shift keying; phase locked loops; 1.5 V; 2.65 V; 22 MW; EDGE; GMS; LIF mode; Laurent approximation; ZIF mode; audio application; audio codec; baseband signal processing; clock jitter suppression; mixed-signal front-end CMOS chip; nonlinear GMSK modulator; Application specific integrated circuits; Baseband; Clocks; Continuous production; Frequency; GSM; Ground penetrating radar; Jitter; Phase locked loops; Signal resolution; 8PSK; Audio CODEC; EDGE; GMSK; GSM; Laurent approximation; baseband signal processing; continuous-time sigma-delta ADC; power control;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.2006.874343