Title :
A 155.52 mbps-3.125 gbps continuous-rate clock and data recovery circuit
Author :
Yang, Rong-Jyi ; Chao, Kuan-Hua ; Hwu, Sy-Chyuan ; Liang, Chuan-Kang ; Liu, Shen-Iuan
Author_Institution :
Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
fDate :
6/1/2006 12:00:00 AM
Abstract :
A 155.52 Mbps-3.125 Gbps continuous-rate clock and data recovery (CDR) circuit using the full-rate bang-bang phase detector is presented. A frequency detector is proposed to eliminate the harmonic locking problem even with a wide range of data rates and its theoretical analysis is also discussed. A quadrature divider is also presented to generate the clocks with accurate quadrature phases. This CDR circuit has been realized in a 0.18-μm CMOS process and its die area is 1.1×0.8 mm2. It consumes 95 mW at the highest bit rate of 3.125 Gbps. It can recover the NRZ data of a 231-1 PRBS with the bit rate ranging from 155.52 Mbps to 3.125Gbps for the incremental frequency acquisition and the NRZ data of a 27-1 PRBS for the decremental frequency acquisition. All the measured bit error rates are less than 10-12.
Keywords :
CMOS digital integrated circuits; digital phase locked loops; phase detectors; synchronisation; 0.18 micron; 155.52 to 3.125E3 Mbits/s; 95 MW; bang-bang phase detector; clock-and-data recovery circuit; frequency detector; harmonic locking problem; phase-locked loop; quadrature divider; Bit error rate; Bit rate; CMOS process; Circuits; Clocks; Detectors; Frequency; Harmonic analysis; Optical signal processing; Phase detection; Bang-bang; clock and data recovery (CDR); frequency detector (FD); phase-locked loop (PLL);
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.2006.874328
