Capacitorless 1T DRAM sensing scheme with automatic reference generation

Author

Blagojevic, Marija ; Kayal, Maher ; Pastre, Marc ; Harik, Louis ; Declercq, Michel J. ; Okhonin, Serguei ; Fazan, Pierre C.

Author_Institution

Ecole Polytech. Fed. de Lausanne, Switzerland

Volume

41

Issue

6

fYear

2006

fDate

6/1/2006 12:00:00 AM

Firstpage

1463

Lastpage

1470

Abstract

To perform a current sensing in capacitorless 1-transistor (1T) DRAMs on SOI, we have developed a sensing scheme with automatic reference generation. The reference current is generated by an adjustable current source. The electrical calibration of the reference current source is performed using a digital-to-analog converter and a successive approximations algorithm. By setting the reference just below the current of the data state "1", the data retention time in the holding mode is maximized. The proposed scheme is evaluated in a 2-kb test chip implemented in a 1-μm partially depleted (PD) SOI process. The measured retention time under holding conditions is higher than 1s. In the continuous read mode, a few hundreds of the read cycles can be performed without a refresh operation. The test chip measures an access time of 25 ns with a read cycle time of 70 ns.

Keywords

DRAM chips; digital-analogue conversion; reference circuits; silicon-on-insulator; 1 s; 25 ns; 70 ns; SOI; automatic reference generation; capacitorless IT DRAM; data retention time; digital-to-analog converter; sensing scheme; Calibration; Capacitors; Circuit testing; Decoding; Manufacturing processes; Random access memory; Semiconductor device measurement; Silicon on insulator technology; Statistical distributions; Time measurement; Adjustable current source; capacitorless 1-transistor DRAM; floating body effect; partially depleted silicon-on-insulator; successive approximations algorithm;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.2006.874357

Filename

1637610