Gallium-arsenide process evaluation based on a RISC microprocessor example

Author

Brown, Richard B. ; Upton, Michael ; Chandna, Ajay ; Huff, Thomas R. ; Mudge, Trevor N. ; Oettel, Richard E.

Author_Institution

Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA

Volume

28

Issue

10

fYear

1993

fDate

10/1/1993 12:00:00 AM

Firstpage

1030

Lastpage

1037

Abstract

The authors evaluate the features of a gallium-arsenide E/D MESFET process in which a 32-b RISC microprocessor was implemented. The design methodology and architecture of this prototype CPU are described. The performance sensitivities of the microprocessor and other large circuit blocks to different process parameters are analyzed, and recommendations for future process features, circuit approaches, and layout styles are made. These recommendations are reflected in the design of a second microprocessor using a more advanced process that achieves much higher density and performance

Keywords

III-V semiconductors; Schottky gate field effect transistors; field effect integrated circuits; gallium arsenide; integrated circuit technology; microprocessor chips; reduced instruction set computing; 32 bit; E/D MESFET process; GaAs; RISC microprocessor; architecture; design methodology; layout styles; performance sensitivities; process parameters; prototype CPU; Circuits; Design methodology; Gallium arsenide; Hardware design languages; MESFETs; Microprocessors; Performance analysis; Prototypes; Reduced instruction set computing; Very large scale integration;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.237518

Filename

237518