A novel Voltage-mode CMOS quaternary logic design

Author

Da Silva, Ricardo Cunha G ; Boudinov, Henri ; Carro, Luigi

Author_Institution

Univ. Fed. do Rio Grande do Sul, Porto Alegre, Brazil

Volume

53

Issue

6

fYear

2006

fDate

6/1/2006 12:00:00 AM

Firstpage

1480

Lastpage

1483

Abstract

This brief presents a novel kind of voltage-mode CMOS design that uses multiple threshold voltage transistors and three power supply lines to implement quaternary logic gates, showing lower power dissipation and using less area than the present voltage-mode quaternary circuits. Inverter, NMIN, and NMAX gates are simulated with the Spice tool using TSMC 0.18-μm technology. The proposed logic circuits overcome the limitations of previous implementations used for multiple-valued logic circuits, such as static power consumption and noise vulnerability.

Keywords

CMOS logic circuits; SPICE; logic CAD; logic gates; 0.18 micron; Spice tool; inverter; lower power dissipation; multiple threshold voltage transistors; multiple-valued logic circuits; quaternary circuits; quaternary logic design; quaternary logic gates; voltage-mode CMOS; CMOS logic circuits; CMOS technology; Circuit simulation; Inverters; Logic circuits; Logic design; Logic gates; Power dissipation; Power supplies; Threshold voltage; Inverter; NMAX; NMIN; multiple-valued logic (MVL) circuits; voltage-mode quaternary CMOS design;

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/TED.2006.874751

Filename

1637648