Title :
Comments on `Totally self-checking CMOS circuit design for breaks and stuck-on faults´
Author :
Bruls, Eric ; Sachdev, Manoj ; Baker, Keith
Author_Institution :
Philips Res. Labs., Eindhoven, Netherlands
fDate :
10/1/1993 12:00:00 AM
Abstract :
The commenters argue that in the above-titled paper by M.S. Cheema and P.K. Lala (ibid., vol.27, no.8, p.1203-6, Aug. 1992) a reference has been wrongly interpreted by the authors, resulting in an incorrect impression of the defect densities. Another problem, concerning the propagation of faults to the final outputs, is also discussed. Furthermore, the commenter points out that the dynamic behavior of the method is not addressed in the original paper and that the design technique presented in the paper requires a high area overhead with which not all possible defects will be detected
Keywords :
CMOS integrated circuits; built-in self test; fault location; integrated circuit testing; integrated logic circuits; logic design; logic testing; CMOS circuit design; breaks; defect densities; design technique; dynamic behavior; fault propagation; stuck-on faults; totally self-checking design; Built-in self-test; Capacitance; Circuit faults; Circuit synthesis; Clocks; Design methodology; Fabrication; Logic; Resists; Voltage;
Journal_Title :
Solid-State Circuits, IEEE Journal of
