Title :
Measurement and Analysis of PD-SOI Static Latches Based on Bistable-Gated-Bipolar Device
Author :
Cheng, Xu ; Duane, Russell
Author_Institution :
Univ. Coll. Cork, Cork
Abstract :
Bistable-gated-bipolar (BGB) device is an impact-ionization based negative differential resistance (NDR) device featuring full process compatibility with CMOS. This paper presents measurement and analysis of the BGB-based static latches fabricated in a standard 0.35 partially depleted silicon-on-insulator (PD SOI) CMOS technology. The experimental results demonstrate the static storage functionality and the minimum standby current of 0.1-1 nA per BGB device for the drain-to-source voltage ranging from 2.0 to 1.6 V. Compared with the conventional CMOS static latch in the same technology, the delay time is shortened by 100 ps, verified by measurement, SPICE simulation and analysis. As the major penalty for speed enhancement, increase in standby current prevents the BGB devices and the associated MOS switches from aggressively scaling and the BGB-based latches are suitable for large-geometry CMOS logic and ultralow-voltage dynamic threshold voltage MOSFET (DTMOS) logic with high switching activity.
Keywords :
CMOS logic circuits; bipolar logic circuits; silicon-on-insulator; BGB; CMOS; DTMOS logic; NDR; PD-SOI static latches; SPICE simulation; bistable-gated-bipolar device; dynamic threshold voltage MOSFET logic; negative differential resistance; silicon-on-insulator; static storage functionality; CMOS logic circuits; CMOS process; CMOS technology; Current measurement; Delay effects; Electrical resistance measurement; Logic devices; Measurement standards; Silicon on insulator technology; Voltage; CMOS digital integrated circuits; flip-flops; negative resistance devices;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.2007.907176
