Low-Power Successive Approximation Converter With 0.5 V Supply in 90 nm CMOS

Author

Gambini, Simone ; Rabaey, Jan

Author_Institution

Univ. of California, Berkeley

Volume

42

Issue

11

fYear

2007

Firstpage

2348

Lastpage

2356

Abstract

We report on the design and characterization of an ultralow-power converter, designed for use in baseband digitization in wireless sensor network radio receivers. The converter uses a successive approximation architecture and operates robustly with a supply voltage as low as 450 mV, overcoming charge leakage limitations. Implemented in a 90 nm CMOS process, this design achieves a figure of merit of 0.14 pJ/Conv.Step for the converter core and shows the integration of a complete data-conversion subsystem, including reference generation, from a 0.5 V supply.

Keywords

CMOS digital integrated circuits; analogue-digital conversion; integrated circuit design; low-power electronics; power convertors; radio receivers; wireless sensor networks; CMOS process; analog-to-digital conversion; baseband digitization; charge leakage; data-conversion subsystem; low-power successive approximation converter; radio receiver; size 90 nm; ultralow-power converter; voltage 0.5 V; wireless sensor network; Analog-digital conversion; Calibration; Capacitance; Circuits; Clocks; Low voltage; Power dissipation; Receivers; Sampling methods; Wireless sensor networks; Analog-to-digital conversion; CMOS; charge leakage; digital calibration; low power; low voltage; subthreshold; successive approximation;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.2007.906210

Filename

4362094