Title :
A 2.5 GHz All-Digital Delay-Locked Loop in 0.13 μm CMOS Technology
Author :
Yang, Rong-Jyi ; Liu, Shen-Iuan
Author_Institution :
Nat. Taiwan Univ., Taipei
Abstract :
A 2.5 GHz, 30 mW, 0.03 mm2, all-digital delay-locked loop (ADDLL) in 0.13 mum CMOS technology is presented. The tri-state digital phase detector suppresses the dithering phenomenon and reduces the output peak-to-peak jitter for a counter-controlled digital DLL. The lattice delay unit has both a small delay step and a fixed intrinsic delay of two nand gates. A modified successive approximation register-controller reduces the locking time and allows the DLL to track the process, voltage, temperature, and load variations. This ADDLL locks in 24 cycles and has a closed-loop characteristic. The measured peak-to-peak jitter is 14 ps at 2.5 GHz.
Keywords :
CMOS digital integrated circuits; delay lock loops; logic gates; phase detectors; CMOS technology; all-digital delay-locked loop; dithering phenomand; frequency 2.5 GHz; nand gates; power 30 mW; register-controller; size 0.13 mum; tri-state digital phase detector; CMOS technology; Clocks; Delay lines; Detectors; Jitter; Lattices; Phase detection; Random access memory; Temperature; Voltage; All-digital; delay-locked loop; modified successive approximation register; tri-state phase detector;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.2007.906183
