DocumentCode :
954684
Title :
Numerical accuracy and hardware tradeoffs for CORDIC arithmetic for special-purpose processors
Author :
Kota, Kishore ; Cavallaro, Joseph R.
Author_Institution :
Dept. of Electr. & Comput. Eng., Rice Univ., Houston, TX, USA
Volume :
42
Issue :
7
fYear :
1993
fDate :
7/1/1993 12:00:00 AM
Firstpage :
769
Lastpage :
779
Abstract :
The coordinate rotation digital computer (CORDIC) algorithm is used in numerous special-purpose systems for real-time signal processing applications. An analysis of fixed-point CORDIC in the Y-reduction mode, which allows computation of the inverse tangent function, shows that unnormalized input values can result in large numerical errors. The authors describe two approaches for tackling the numerical accuracy problem. The first approach builds on a fixed-point CORDIC unit and eliminates the problem by including additional hardware for normalization. A method for integrating the normalization operation with the CORDIC iterations for efficient implementation in O(n1.5) hardware is provided. The second solution to the accuracy problem is to use a floating-point CORDIC unit but reduce the implementation complexity by using a hybrid architecture. Arguments to support the use of such an architecture in certain special-purpose arrays are presented
Keywords :
digital arithmetic; signal processing; CORDIC arithmetic; Y-reduction mode; coordinate rotation digital computer; floating-point CORDIC; hardware tradeoffs; hybrid architecture; implementation complexity; inverse tangent function; numerical accuracy; real-time signal processing; special-purpose arrays; special-purpose processors; Application software; Computer architecture; Computer errors; Digital arithmetic; Digital signal processing chips; Error analysis; Hardware; Navigation; Signal processing algorithms; Very large scale integration;
fLanguage :
English
Journal_Title :
Computers, IEEE Transactions on
Publisher :
ieee
ISSN :
0018-9340
Type :
jour
DOI :
10.1109/12.237718
Filename :
237718
Link To Document :
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