Interlock collapsing ALU´s

Author

Vassiliadis, Stamatis ; Phillips, James ; Blaner, Bart

Author_Institution

Endicott Eng. Lab., IBM, NY, USA

Volume

42

Issue

7

fYear

1993

fDate

7/1/1993 12:00:00 AM

Firstpage

825

Lastpage

839

Abstract

A device capable of executing interlocked fixed point arithmetic logic unit (ALU) instructions in parallel with other instructions causing the execution interlock is presented. The device incorporates the design of a 3-1 ALU and can execute two´s complement, unsigned binary, and binary logical operations. It is shown that status for ALU operations using a 3-1 ALU can be determined in a parallel fashion, resulting in the compliance of the proposed device with predetermined architectural behavior of single instruction execution. The device requires no more logic stages than does a 3-1 binary adder using a carry-save adder (CSA) followed by a carry-lookahead adder (CLA) design. Design considerations using a commonly available CMOS technology are also reported, indicating that the device will not increase the machine cycle of an implementation. It is suggested that the device can maintain full architectural compatibility

Keywords

CMOS integrated circuits; adders; digital arithmetic; parallel processing; CMOS technology; architectural compatibility; binary logical operations; carry-lookahead adder; carry-save adder; interlocked fixed point arithmetic logic unit; machine cycle; single instruction execution; two´s complement; unsigned binary; CMOS logic circuits; CMOS technology; Degradation; Hardware; Hazards; Laboratories; Logic design; Logic devices; Parallel machines; Pipelines;

fLanguage

English

Journal_Title

Computers, IEEE Transactions on

Publisher

ieee

ISSN

0018-9340

Type

jour

DOI

10.1109/12.237723

Filename

237723