Title :
LT-RTPG: a new test-per-scan BIST TPG for low switching activity
Author :
Wang, Seongmoon ; Gupta, Sandeep K.
Author_Institution :
NEC Labs. America, Princeton, NJ, USA
Abstract :
A new built-in self-test (BIST) test pattern generator (TPG) design, called low-transition random TPG (LT-RTPG), is presented. An LT-RTPG is composed of a linear feedback shift register (LFSR), a κ-input AND gate, and a T flip-flop. When used to generate test patterns for test-per-scan BIST, it decreases the number of transitions that occur during scan shifting and, hence, decreases switching activity during testing. Various properties of LT-RTPGs are identified and a methodology for their design is presented. Experimental results demonstrate that LT-RTPGs designed using the proposed methodology decrease switching activity during BIST by significant amounts while providing high fault coverage.
Keywords :
automatic test pattern generation; built-in self test; flip-flops; integrated circuit testing; logic gates; shift registers; switching circuits; BIST TPG; LFSR; LT-RTPG; T flip-flop; built-in self-test; k-input AND gate; linear feedback shift register; low switching activity; low-transition random TPG; test pattern generator; Automatic testing; Built-in self-test; Circuit faults; Circuit testing; Flip-flops; Inductance; Linear feedback shift registers; Semiconductor device noise; Switching circuits; Test pattern generators; Built-in self-test (BIST); heat dissipation during testing; switching activity; test pattern generator (TPG); testing;
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
DOI :
10.1109/TCAD.2005.855927