Title :
Calculation method to obtain worst-case static noise margins of logic circuits
Author_Institution :
Philips Research Laboratories, Eindhoven, Netherlands
Abstract :
A relatively simple calculation method is introduced using the flip-flop method, and by using the criterion that, with marginal static noise applied to the flip-flop, the loopgain is 1. As an example, the worst-case static series voltage noise margin of I2L is calculated.
Keywords :
bipolar transistor circuits; logic design; noise; I2L; calculation method; logic circuits; series voltage noise; worst case static noise margin flip flop method;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:19800199
