Practical scheduling and line optimization technology for ASIC manufacturing lines

The problem of obtaining quick product turnaround time (TAT) as well as high throughput on application specific integrated circuit (ASIC) manufacturing lines, is addressed. To achieve both, efficient lot management and line operation are required. An automatic scheduler and method of customization to increase scheduling efficiency, which have been developed for satisfying these requirements, simultaneously are described. Simulations with the scheduler yielded the concept of line performance curves (LPCs). Based on the techniques discussed, a line management algorithm that places emphasis on TAT has been developed. It employs a due date management chart (DMC) and a lot release control chart (LCC). These developments make possible huge improvements in the efficiency of ASIC manufacturing lines