Title :
The Gmicro/500 superscalar microprocessor with branch buffers
Author :
Uchiyama, Kunio ; Arakawa, Fumio ; Narita, Susumu ; Aoki, Hirokazu ; Kawasaki, Ikuya ; Matsui, Shigezumi ; Yamamoto, Mitsuyoshi ; Nakagawa, Norio ; Kudo, Ikuo
Author_Institution :
Hitachi Ltd., Tokyo, Japan
Abstract :
The Gmicro/500, which features a RISC-like dual-pipeline structure for high-speed execution of basic instructions and represents a significant advance for the TRON architecture, is presented. Upwardly-object-compatible with earlier members of the Gmicro series, this microprocessor uses resident dedicated branch buffers to greatly enhance branch instruction execution speed. Its microprograms simultaneously use dual execution blocks to execute high-level language instructions effectively. Fabricated with a 0.6- mu m CMOS technology on a 10.9-mm*16-mm die, the chip operates at 50/66 MHz and achieves a processing rate of 100/132 MIPS.<>
Keywords :
CMOS integrated circuits; microprocessor chips; reduced instruction set computing; 0.6 micron; 100 to 132 MIPS; 50 to 66 MHz; CMOS technology; Gmicro/500 superscalar microprocessor; RISC-like dual-pipeline structure; TRON architecture; branch buffers; branch instruction execution speed; dual execution blocks; high-level language instructions; high-speed execution; Buffer storage; CMOS process; CMOS technology; Clocks; Computer architecture; Costs; Frequency; Microprocessors; Packaging; Power dissipation;
Journal_Title :
Micro, IEEE
