• DocumentCode
    956005
  • Title

    SPAR: a schematic place and route system

  • Author

    Frezza, Stephen T. ; Levitan, Steven P.

  • Author_Institution
    Dept. of Electr. Eng., Pittsburgh Univ., PA, USA
  • Volume
    12
  • Issue
    7
  • fYear
    1993
  • fDate
    7/1/1993 12:00:00 AM
  • Firstpage
    956
  • Lastpage
    973
  • Abstract
    An approach to the automatic generation of schematic diagrams from circuit descriptions is presented. The heuristics that make up the system are based on two principles of schematics readability: functional identification and traceability. SPAR´s generation process is broken into five distinct phases: partitioning the netlist, placement of components on the page, global routing, local routing, and the addition of I/O modules. All phases of the generation process use a two-dimensional space management technique based on virtual tile spaces. The global router is guided by a cost function consisting of both congestion and wirelength estimates. The local router uses a constraint-propagation technique to optimize the traceability of lines through congested areas. The data structures and algorithms used allow the system to support incremental additions to the schematic without complete regeneration. A technique for evaluating the quality of schematic drawings is described and applied to the present results
  • Keywords
    circuit diagrams; circuit layout CAD; network routing; wiring; I/O modules; SPAR; automatic generation; circuit descriptions; congestion; constraint-propagation technique; cost function; data structures; functional identification; global routing; local routing; partitioning; placement; schematic diagrams; schematic place and route system; traceability; two-dimensional space management technique; virtual tile spaces; wirelength estimates; Constraint optimization; Cost function; Data structures; Displays; Hardware; Humans; Integrated circuit interconnections; Routing; Signal design; Tiles;
  • fLanguage
    English
  • Journal_Title
    Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0278-0070
  • Type

    jour

  • DOI
    10.1109/43.238032
  • Filename
    238032