Application of self-aligned CoSi2 interconnection in submicrometer CMOS transistors

CoSi₂ interconnection layers of 0.14-0.40- mu m thickness were applied in a self-aligned manner to 0.75- mu m-gate-length n-channel and p-channel transistors in a complete CMOS device fabrication flow. The sheet resistance above the active regions ranged from 1.6 to as low as 0.46 Omega /square for the four CoSi₂ thicknesses examined. Using an Al-Cu/TiW metallization, the resistance per contact for 1- mu m-diameter openings to CoSi₂ was + (B)/n and approximately=90% for n⁺ (As)/p did not adversely affect the measured reverse-bias leakage for transistor gain performance. Furthermore, CoSi₂ layers were found compatible with the high-temperature annealing (902 degrees C) of an oxide overlayer, used to achieve some planarization of the device topography, without degradation in electrical performance.