• DocumentCode
    956053
  • Title

    Shadowing effects due to tilted arsenic source/drain implant

  • Author

    Krieger, Gadi ; Spadini, Gianpaolo ; Cuevas, Peter P. ; Schuur, John

  • Author_Institution
    VLSI Technol. Inc., San Jose, CA, USA
  • Volume
    36
  • Issue
    11
  • fYear
    1989
  • fDate
    11/1/1989 12:00:00 AM
  • Firstpage
    2458
  • Lastpage
    2461
  • Abstract
    The extent of n+ source/drain implant shadowing by the LDD (lightly doped drain) oxide sidewall spacer was studied for the commonly used 7 degrees wafer-to-implant beam tilt. A clear asymmetry in substrate current characteristics was observed between normal and reverse polarity, despite the use of 0 degrees tilt for the n- LDD implant. The results suggest that 0 degrees tilt should be used for both n- (LDD) and n+ (source/drain) implants.
  • Keywords
    arsenic; insulated gate field effect transistors; ion implantation; semiconductor technology; LDD oxide sidewall spacer; MOS transistors; Si:As; n+ source/drain implant shadowing; normal polarity; reverse polarity; substrate current characteristics; wafer-to-implant beam tilt; Constraint optimization; Current measurement; Degradation; Electric resistance; Hot carrier effects; Hot carriers; Implants; Ion beams; MOSFETs; Shadow mapping;
  • fLanguage
    English
  • Journal_Title
    Electron Devices, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9383
  • Type

    jour

  • DOI
    10.1109/16.43667
  • Filename
    43667
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=956053