Application of electrical effective channel length and external resistance measurement techniques to a submicrometer CMOS process

The practical applications and limitations of four methods for extracting the effective channel length (L_eff) and series resistance (R_ext) parameters for MOS devices are studied. The methods are: GD (gate drive) using fixed-current V_t or GD(I_ds); SBGD (substrate-bias GD) using fixed-current V_t or SBGD (I_ds); GD using maximum slope V_t or GD (G_m); and SBGD using maximum slope V_t or SBGD (G_m). Conventional and two LDD (lightly doped drain) structures fabricated in a submicrometer CMOS process are used. The results indicate that all the extraction methods are applicable to both n-channel and p-channel devices, although some are only valid over a small range of gate biases. Inconsistencies in applying V_t calculations to the extraction equations set a lower limit for V_gst of approximately 0.5 V, while the upper limit of 2.0-4.0 V arises due to imprecision in R_ds measurements influencing the double regression steps involved in the techniques. The SBGD (I_ds) method was applicable over a wider range of bias conditions than the other techniques analyzed and is easier to implement.