A unified global and local interconnect test scheme for Xilinx XC4000 FPGAs

Author

Sun, Xiaoling ; Trouborst, Pieter

Author_Institution

Dept. of Electr. & Comput. Eng., Univ. of Alberta, Edmonton, Alta., Canada

Volume

Issue

fYear

2004

fDate

4/1/2004 12:00:00 AM

Firstpage

368

Lastpage

377

Abstract

This paper presents a unified global and local interconnect testing scheme for field programmable gate arrays. Adjacency graphs are used to model interconnect resources and their test requirements, and an efficient computer algorithm for automatic derivation of test configurations is given. A device configuration generation tool was developed to reduce the test development cost.

Keywords

field programmable gate arrays; integrated circuit interconnections; integrated circuit testing; FPGA; Xilinx XC4000 FPGAs; adjacency graphs; automatic test configuration derivation; computer algorithm; device configuration generation tool; field programmable gate arrays; global-local interconnect testing; interconnect resource modeling; test algorithm; test development; Automatic testing; Built-in self-test; Circuit testing; Field programmable gate arrays; Integrated circuit interconnections; Logic devices; Programmable logic arrays; Sun; System testing; Wire;

fLanguage

English

Journal_Title

Instrumentation and Measurement, IEEE Transactions on

Publisher

ieee

ISSN

0018-9456

Type

jour

DOI

10.1109/TIM.2003.822718

Filename

1284867

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=956483