A Novel Single Polysilicon EEPROM Cell With a Polyfinger Capacitor

In this letter, we describe a novel single polysilicon electrically erasable read-only memory cell with polyfinger capacitor for the control gate (CG). A finger-type capacitor structure with CoSi₂ is applied to a floating gate and the CG of the proposed cell. The proposed cell is fabricated by using a 0.18-mum standard logic process. The intergate dielectrics of the proposed cell are formed by a conventional lightly doped drain spacer material that is composed of SiO₂ and Si₃N₄ to avoid any process modification. A Fowler-Nordheim tunneling method is applied for the programming and erasing of the cell. Endurance characteristics of up to 120 000 cycles are demonstrated. The proposed cell shows acceptable data retention characteristics.