Timing uncertainties of A/D converters: theoretical study and experiments

For high-speed analog-to-digital converters, sampling jitter is a relevant parameter, limiting over-all performances of mixed-signal systems. Among the several contributions usually encountered in such systems, this paper focuses on the one generated by the clock interface and sampling circuits of the converter. To have an accurate description of this "internal" sampling jitter, a theoretical model is first introduced and then experimentally validated.