• DocumentCode
    956774
  • Title

    Bit synchronisation in Gbit/s range using dual gate GaAs m.e.s.f.e.t.s

  • Author

    Beneking, H. ; Filensky, W. ; Ponse, F.

  • Author_Institution
    Aachen Technical University, Institute of Semiconductor Electronics, Aachen, West Germany
  • Volume
    16
  • Issue
    14
  • fYear
    1980
  • Firstpage
    543
  • Lastpage
    544
  • Abstract
    Bit synchronisation at 1 and 2 Gbit/s including pulse width reduction is achieved using dual gate GaAs m.e.s.f.e.t.s. Circuits and time behaviour of input-, clock- and output signals are shown.
  • Keywords
    Schottky gate field effect transistors; field effect transistor circuits; pulse shaping circuits; synchronisation; Gbit/s range; bit synchronisation; clock signals; dual gate GaAs MESFET; input signals; output signals; time behaviour;
  • fLanguage
    English
  • Journal_Title
    Electronics Letters
  • Publisher
    iet
  • ISSN
    0013-5194
  • Type

    jour

  • DOI
    10.1049/el:19800378
  • Filename
    4244149
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=956774