Performance Enhancement in Uniaxial Strained Silicon-on-Insulator N-MOSFETs Featuring Silicon–Carbon Source/Drain Regions

We report the demonstration of a novel strained silicon-on-insulator N-MOSFET featuring silicon-carbon (Si_1-yC_y) source and drain (S/D) regions, tantalum nitride metal gate, and hafnium-aluminum oxide high-k gate dielectric. Due to the lattice mismatch between Si_0.99C_0.01 S/D stressors and Si, a lateral tensile strain is induced in the transistor channel, leading to substantial electron mobility enhancement. At a fixed OFF-state leakage of 100 nA/mum, the Sii-j/C_1-yC_y S/D N-MOSFET having a width of 4.7 mum achieves a drive current Josat enhancement of 16% over a control N-MOSFET. This iDsat enhancement, which is primarily attributed to strain-induced mobility improvement, is found to increase with decreasing gate length LG due to an increased strain level in the transistor channel as the Si_1-yC_y S/D stressors are placed in closer proximity. Slightly improved series resistance with Si_1-yC_y S/D regions in a strained N-MOSFET accounted for approximately 2% I_Dsat gain. In addition, a reduction of device width is found to reduce the drive current enhancement of the N-MOSFETs due to the presence of a transverse compressive strain in the transistor channel induced by the isolation regions.