Title :
A New Gate-Charging Protection Strategy for Transistors in Integrated-Circuit Test Chips and Products
Author :
Lin, Wallace ; Smudski, Jan
Author_Institution :
Intel Corp., Santa Clara
Abstract :
This paper presents a new gate-charging protection strategy for transistors in integrated-circuit (IC) test chips and products. The strategy, using a low-threshold-voltage protection device (PD) of the highest voltage class (i.e., with the thickest available gate oxide) in any given process technology, is capable of providing full charging protection for transistors of all voltage classes during back-end plasma-involved manufacturing process. In conjunction with a method that globally turns off the PDs, the strategy also minimizes the protection-device-induced leakages during electrical tests or circuit operation. This new gate-charging protection strategy can benefit the design and manufacturing for the next-generation IC test chips and products, in particular for circuit products emphasized on low voltage and current and low power consumption.
Keywords :
field effect transistors; integrated circuit testing; low-power electronics; microprocessor chips; MOSFET; back end plasma involved manufacturing process; depletion mode; enhancement mode; gate charging protection strategy; gate oxide; integrated circuit test chips; layout space; low threshold voltage protection device; power consumption; Circuit testing; Energy consumption; Integrated circuit technology; Integrated circuit testing; Low voltage; Manufacturing processes; Plasma devices; Plasma materials processing; Protection; Transistors; CMOS; Charging protection; MOSFET; circuit; depletion mode; enhancement mode; gate oxide; layout space; leakage; low current; low power; low voltage; parasitic; plasma; power consumption; product; test chip; threshold voltage; transistor;
Journal_Title :
Electron Devices, IEEE Transactions on
DOI :
10.1109/TED.2007.907163
