Design Considerations for Sub-90-nm Split-Gate Flash-Memory Cells

This paper presents a systematic methodology to design efficient sub-90-nm split-gate Flash-memory cells and optimize the cell performance within the presently known scaling constraints. The device-simulation results show that the high-performance sub-90-nm split-gate cells can be realized by a proper optimization of the channel and asymmetric halo-doping profiles and shallow source/drain junctions. In this paper, the halo-and channel-doping profiles were optimized to achieve the target drain-programming voltage V_sp = 6.5 V for an efficient cell programming, whereas keeping the breakdown voltage BV > V_sp with tolerable leakage currents. It is shown that, using the properly optimized technology parameters, 65-nm split-gate Flash memory can be achieved with cell-read current, I_r1 ap 235 mum, programmed cell-leakage current, Ir₀ < 2.2 nA/ mum at the read condition, time-to-program ap 30 mus, and time-to-erase ap 40 mus. This paper clearly demonstrates the feasibility of high-performance 65-nm split-gate Flash-memory cells.