• DocumentCode
    957144
  • Title

    Enhancement of Drain Current in Planar MOSFETs by Dopant Profile Engineering Using Nonmelt Laser Spike Annealing

  • Author

    Shima, Akio ; Mine, Toshiyuki ; Torii, Kazuyoshi ; Hiraiwa, Atsushi

  • Author_Institution
    Hitachi, Ltd., Kokubunji
  • Volume
    54
  • Issue
    11
  • fYear
    2007
  • Firstpage
    2953
  • Lastpage
    2959
  • Abstract
    We investigated the effect of dopant profile engineering in planar MOSFETs, in which activation annealing was done using only nonmelt laser spike annealing (LSA). Device performance was 10% and 20% better compared to that when conventional LSA and rapid thermal annealing (RTA) are used, respectively. We achieved this by reengineering the following: 1) angle implantation in the extension of an nFET; 2) germanium preamorphization implantation in the extension of a pFET; 3) halo implantation with lower energy and smaller tilt angle; 4) deep source/drain by two-step implantation, and 5) counter implantation adjusted to the halo conditions. Hot carrier degradation was also reduced to an RTA-comparable level by halo profile engineering. Thus, we show that a submillisecond LSA is a promising technique for the fabrication of ultrashallow junctions for the 45-nm technology node and beyond and that a dopant profile engineering taking into account the minimal diffusion length of LSA is required to bring out the best device performance.
  • Keywords
    MOSFET; elemental semiconductors; germanium; laser beam annealing; rapid thermal annealing; activation annealing; angle implantation; counter implantation; dopant profile engineering; drain current; germanium preamorphization implantation; halo implantation; nFET; nonmelt laser spike annealing; pFET; planar MOSFET; rapid thermal annealing; ultrashallow junctions fabrication; Counting circuits; Germanium; Hot carriers; Implants; Lamps; MOSFETs; Rapid thermal annealing; Temperature; Thermal resistance; Very large scale integration; CMOS integrated circuits; junctions; laser annealing; source/drain (S/D) extensions (SDEs); strained silicon; very-large-scale integration (VLSI);
  • fLanguage
    English
  • Journal_Title
    Electron Devices, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9383
  • Type

    jour

  • DOI
    10.1109/TED.2007.906972
  • Filename
    4367615