Title :
A high-speed BiCMOS tristate buffer
Author :
Kuo, J.B. ; Liao, H.J.
Author_Institution :
Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
fDate :
7/1/1993 12:00:00 AM
Abstract :
A high-speed BiCMOS tristate buffer with a single bipolar device pull-up structure for driving a large capacitive load is presented. According to SPICE simulation results, the buffer, which occupies about an identical area, has a 2×improvement in delay time as compared to the CMOS tristate buffer
Keywords :
BiCMOS integrated circuits; buffer circuits; integrated logic circuits; BiCMOS tristate buffer; SPICE simulation; bipolar device pull-up structure; capacitive load; delay time; high-speed; BiCMOS integrated circuits; CMOS logic circuits; Delay effects; Logic circuits; Logic design; Logic gates; MOS devices; Microprocessors; SPICE; Very large scale integration;
Journal_Title :
Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on
