Title :
Estimating architectural resources and performance for high-level synthesis applications
Author :
Sharma, Alok ; Jain, Rajiv
Author_Institution :
Amdahl Corp., Sunnyvale, CA, USA
fDate :
6/1/1993 12:00:00 AM
Abstract :
The authors present a solution to the following problems related to architectural synthesis. (1) Given an input specification and a performance constraint, determine a lower bound number of resources (active and interconnect) required to execute the data flow graph while satisfying the performance constraint. (2) Determine a lower bound performance for executing an input specification for a given number of resources (active and interconnect). These bounds are close to the actual designs synthesized by several existing systems.<>
Keywords :
logic CAD; parallel architectures; architectural resources; data flow graph; high-level synthesis applications; input specification; performance constraint; Algorithm design and analysis; Character generation; Clocks; Delay estimation; Flow graphs; High level synthesis; Processor scheduling; Upper bound; Very large scale integration;
Journal_Title :
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
