Title :
M*N Booth encoded multiplier generator using optimized Wallace trees
Author :
Fadavi-Ardekani, Jalil
Author_Institution :
AT&T Bell Lab., Allentown, PA, USA
fDate :
6/1/1993 12:00:00 AM
Abstract :
The architecture of a design method for an M-bit by N-bit Booth encoded parallel multiplier generator are discussed. An algorithm for reducing the delay inside the branches of the Wallace tree section is explained. The final step of adding two N+or-M-1-bit numbers is done by an optimal carry select adder stage. The algorithm for optimal partitioning of the N+or-M-1-bit adder is also presented.<>
Keywords :
adders; carry logic; logic design; multiplying circuits; trees (mathematics); Booth encoded parallel multiplier generator; adder; delay; optimal carry select adder stage; optimal partitioning; optimized Wallace trees; Adders; Circuit testing; Delay; Design methodology; Design optimization; Flow graphs; Partitioning algorithms; Pipelines; Variable speed drives; Very large scale integration;
Journal_Title :
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
