The Siemens high-level synthesis system CALLAS

Author

Biesenack, Jörg ; Koster, Michael ; Langmaier, Anton ; Ledeux, Stephane ; März, Sabine ; Payer, Michael ; Pilsl, Michael ; Rumler, Steffen ; Soukup, Holger ; Wehn, Norbert ; Duzy, Peter

Author_Institution

Corp. Res. & Dev., Siemens AG, Munich, Germany

Volume

1

Issue

3

fYear

1993

Firstpage

244

Lastpage

253

Abstract

In this paper we present the Siemens high-level synthesis system CALLAS and describe its design methodology and synthesis strategy. It supports the synthesis of control-dominated applications and uses a VHDL subset for the algorithmic specification. Its main feature can be characterized as "What you simulate is what you synthesize." This principle permits a validation of the synthesis results by simulation or even formal verification. CALLAS has been successfully applied on real designs which were implemented in silicon. These examples demonstrate that CALLAS fulfils the constraints and objectives of a hardware designer. The circuits are comparable in quality to results achieved by synthesis starting at the register-transfer-level.<>

Keywords

VLSI; circuit CAD; logic CAD; specification languages; CAD; CALLAS; Siemens; VHDL subset; algorithmic specification; control-dominated applications; design methodology; formal verification; high-level synthesis system; synthesis strategy; Circuit simulation; Circuit synthesis; Control system synthesis; Design automation; Design methodology; Formal verification; Hardware design languages; High level synthesis; Logic design; Silicon;

fLanguage

English

Journal_Title

Very Large Scale Integration (VLSI) Systems, IEEE Transactions on

Publisher

ieee

ISSN

1063-8210

Type

jour

DOI

10.1109/92.238438

Filename

238438