Title :
An Error-Detecting Binary Adder: A Hardware-Shared Implementation
Author :
Gaddess, Terry G.
Author_Institution :
Coordinated Science Laboratory, University of Illinois, Urbana, Ill. 61801.; Texas Instruments, Inc., Dallas, Tex. 75222.
Abstract :
A design for a binary adder-checker system which employs residue codes to detect any error resulting from a single fixed fault is presented. In an adder, special functional relationships must exist, regardless of the particular logical realization. Consequently, for adders with either serial or parallel carry propagation, the worst possible error can be described precisely. Certain residue codes may then be used to detect that error by means of a simple checking algorithm with a minimnum of extra circuitry.
Keywords :
Adders; Circuit faults; Circuit testing; Computer errors; Error correction; Fault detection; Feeds; Logic design; Parallel carry propagation; residue codes; self-checking implementation; serial carry propagation; single permanent fault; worst possible errors;
Journal_Title :
Computers, IEEE Transactions on
DOI :
10.1109/TC.1970.5008897