DocumentCode :
958136
Title :
An Error-Detecting Binary Adder: A Hardware-Shared Implementation
Author :
Gaddess, Terry G.
Author_Institution :
Coordinated Science Laboratory, University of Illinois, Urbana, Ill. 61801.; Texas Instruments, Inc., Dallas, Tex. 75222.
Issue :
1
fYear :
1970
Firstpage :
34
Lastpage :
38
Abstract :
A design for a binary adder-checker system which employs residue codes to detect any error resulting from a single fixed fault is presented. In an adder, special functional relationships must exist, regardless of the particular logical realization. Consequently, for adders with either serial or parallel carry propagation, the worst possible error can be described precisely. Certain residue codes may then be used to detect that error by means of a simple checking algorithm with a minimnum of extra circuitry.
Keywords :
Adders; Circuit faults; Circuit testing; Computer errors; Error correction; Fault detection; Feeds; Logic design; Parallel carry propagation; residue codes; self-checking implementation; serial carry propagation; single permanent fault; worst possible errors;
fLanguage :
English
Journal_Title :
Computers, IEEE Transactions on
Publisher :
ieee
ISSN :
0018-9340
Type :
jour
DOI :
10.1109/TC.1970.5008897
Filename :
5008897
Link To Document :
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