DocumentCode
958147
Title
Interface optimization for concurrent systems under timing constraints
Author
Filo, David ; Ku, David C. ; Coelho, Claudionor N., Jr. ; De Micheli, Giovanni
Author_Institution
Center for Integrated Syst., Stanford Univ., CA, USA
Volume
1
Issue
3
fYear
1993
Firstpage
268
Lastpage
281
Abstract
The scope of most high-level synthesis efforts to date has been at the level of a single behavioral model represented as a control/data-flow graph. The communication between concurrently executing processes and its requirements in terms of timing and resources have largely been neglected. This restriction limits the applicability of most existing approaches for complex system designs. This paper describes a methodology for the synthesis of interfaces in concurrent systems under detailed timing constraints. The authors model interprocess communication using blocking and nonblocking messages. They show how the relationship between messages over time can be abstracted as a constraint graph that can be extracted and used during synthesis. They describe a novel technique called interface matching that minimizes the interface cost by scheduling each process with respect to timing information of other processes communicating with it. By scheduling the completion of operations, some blocking communication can be converted to nonblocking while ensuring the communication remains valid. To further reduce hardware costs, the authors describe the synthesis of interfaces on shared physical media. They show how this sharing can be increased through rescheduling and serialization of the communication. In addition to systematically reducing the interface synchronization cost, this approach permits analysis on the timing consistency of interprocess communication.<>
Keywords
VLSI; circuit CAD; concurrent engineering; graph theory; logic CAD; VLSI; behavioral model; blocking communication; complex system designs; concurrent systems; constraint graph; control/data-flow graph; high-level synthesis; interface cost; interface matching; interface synchronization cost; interprocess communication; logic CAD; scheduling; serialization; shared physical media; timing consistency; timing constraints; Constraint optimization; Control system synthesis; Costs; Graphics; Hardware; High level synthesis; Image edge detection; Image enhancement; Senior members; Timing;
fLanguage
English
Journal_Title
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
Publisher
ieee
ISSN
1063-8210
Type
jour
DOI
10.1109/92.238441
Filename
238441
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