Title :
Mathematical ``Lower Bounds´´ and the Logic Circuit Designer
Author :
Farber, A. S. ; Schlig, E. S.
Author_Institution :
IBM Watson Research Ctr., Yorktown Heights, N. Y.; Responsive Data Processing Corporation, Mt, Kisco, N. Y.
Abstract :
The use of published theorems on least times to perform arithmetic operations as aids in optimizing logic circuit designs is discussed. An illustrative example is presented involving the optimum maximum fan-in of circuits in a binary adder.
Keywords :
Adders; Arithmetic; Computer aided instruction; Delay; Design optimization; Equations; Hardware; Logic circuits; Logic design; Polynomials; Arithmetic and logic units; computer systems hardware; electronic digital computers; logic circuits; logic design;
Journal_Title :
Computers, IEEE Transactions on
DOI :
10.1109/TC.1970.5008905
