Direct measurement of hot-carrier stress effects on CMOS circuit performance

Summary form only given. A novel test structure is proposed for direct study of circuit performance changes under various hot-carrier stress conditions. This test structure permits the effects of DC or AC stress on circuit parameters such as noise margins, gate delay, etc. to be evaluated and correlated to the degradation in the characteristics of individual component MOSFETs. In order to stress an isolated MOS device within a circuit and measure the circuit parameters before and after stress, two transistors are added to a standard CMOS inverter. These modified CMOS inverters can be configured into any appropriate logic gate configuration. With proper biasing, the circuit has two operational modes: (1) a hot-carrier stress mode where inverters are isolated from each other and the component device can be stressed from external bias; (2) a circuit measurement mode where the external bias paths are turned off and the output of the inverter can be directed to the input of the next stage. The resultant degradations in peak transconductance of NMOS devices are compared to the shifts in noise margin from the CMOS inverters. Both peak transconductance and noise margin show power-law dependences on stress time.