High speed and compact CMOS circuits with multi-pillar surrounding gate transistors

Summary form only given. In order to overcome the scaling limitations on planar transistors for future LSIs, the authors propose a novel surrounding gate transistor (SGT), whose gate electrode surrounds multipillar silicon islands. The new SGT offers large drain currents even in a very small occupied area. The large channel width is achieved by using all the sidewalls of the crowded multipillar silicon islands as the channel regions. Owing to this multichannel structure, a transistor with extremely small occupied area and sufficient drivability can be obtained. The small occupied area and the mesh-structured gate electrode lead to small gate electrode RC delay and small junction capacitance, resulting in very high-speed operation, contrary to the cases of the planar transistor and the conventional SGT. A new SGT CMOS inverter chain was fabricated. The propagation delay is reduced to 20% of that for the case of the planar transistors. This new SGT is extremely attractive for future high-speed ULSI devices.