On the lower bound to the VLSI complexity of number conversion from weighted to residue representation

Author

Alia, Giuseppe ; Martinelli, Enrico

Author_Institution

Dipartimento di Ingegneria dell´´Inf, Pisa Univ., Italy

Volume

42

Issue

8

fYear

1993

fDate

8/1/1993 12:00:00 AM

Firstpage

962

Lastpage

967

Abstract

A lower bound AT²=Ω(n²) for the conversion from positional to residue representation is derived according to VLSI complexity theory, and existing solutions for the same problem are briefly reviewed in the light of such a bound. A VLSI system is proposed, one that operates according to a pipeline scheme and works asymptotically emulating an optimal structure, independently of residue number system parameters. This solution has been applied to a design of specific size (64-b input stream), and it has been found that a single CMOS custom chip can implement the design with a throughput of one residue representation every 30-40 ns

Keywords

CMOS integrated circuits; VLSI; computational complexity; digital arithmetic; VLSI complexity; lower bound; number conversion; optimal structure; pipeline scheme; residue representation; single CMOS custom chip; weighted representation; CMOS technology; Complexity theory; Costs; Digital arithmetic; Digital signal processing; Digital systems; Pipeline processing; Signal processing; Throughput; Very large scale integration;

fLanguage

English

Journal_Title

Computers, IEEE Transactions on

Publisher

ieee

ISSN

0018-9340

Type

jour

DOI

10.1109/12.238486

Filename

238486