Test-pattern generation based on Reed-Muller coefficients

Author

Ortega, Julio ; Ruiz, Antonio Lloris ; Prieto, Alberto ; Pelayo, Francisco J.

Author_Institution

Departamento de Electronica y Tecnologia de Computadores, Granada Univ., Spain

Volume

42

Issue

8

fYear

1993

fDate

8/1/1993 12:00:00 AM

Firstpage

968

Lastpage

980

Abstract

Reed-Muller coefficients are used to generate a test-pattern selection procedure for detecting single stuck-at faults. This procedure is based on the heuristics deduced from the way in which the spectral coefficients are affected by such faults. The changes that the spectral coefficients undergo are also compared with the fault models used most frequently to model defects in combinational circuits. The proposed pattern-generating procedure does not need a simulation of the circuit for each of the possible stuck-at faults, and its complexity is proportional to the number of gates in the circuit. The proportionality constant increases exponentially as the number of inputs in the circuit increases. To evaluate the performance of the proposed method, its application to some benchmark circuits, including the ALU 74181, is presented

Keywords

computational complexity; logic testing; ALU 74181; Reed-Muller coefficients; benchmark circuits; combinational circuits; complexity; heuristics; pattern-generating procedure; single stuck-at faults; spectral coefficients; test pattern generation; test-pattern selection procedure; Built-in self-test; Circuit faults; Circuit testing; Digital circuits; Electrical fault detection; Fault detection; Logic gates; Logic testing; Performance evaluation; Test pattern generators;

fLanguage

English

Journal_Title

Computers, IEEE Transactions on

Publisher

ieee

ISSN

0018-9340

Type

jour

DOI

10.1109/12.238487

Filename

238487