Abstract :
With the projected growth in demand for bandwidth and telecommunication services will come the requirement for a multiservice backbone network of far greater efficiency, capacity, and flexibility than ISDN (integrated-services digital network) is able to satisfy. This class of network has been termed the broadband ISDN, and the design of the switching nodes of such a network is the subject of much research. The author investigates one possible solution. The design and performance, for multiservice traffic, is presented for a fast packet switch based on a nonbuffered, multistage interconnection network. It is shown that for an implementation in current CMOS technology, operating at 50 MHz, switches with a total traffic capacity of up to 150 Gb/s can be constructed. Furthermore, if the reserved service traffic load is limited on each input port to a maximum of 80% of switch port saturation, then a maximum delay across the switch of on the order of 100 μs can be guaranteed, for 99% of the reserved service traffic, regardless of the unreserved service traffic load
Keywords :
CMOS integrated circuits; ISDN; broadband networks; packet switching; switching circuits; telecommunication services; telecommunication traffic; 150 Gbit/s; 50 MHz; CMOS technology; broadband ISDN; delay; fast packet switch; integrated services backbone network; multiservice traffic; multistage interconnection network; switching nodes; telecommunication services; traffic load; Bandwidth; CMOS technology; ISDN; Intserv networks; Packet switching; Spine; Switches; Telecommunication services; Telecommunication switching; Telecommunication traffic;
